module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);

    wire	[8:0]	num;
    
    assign num = a + b;
    assign s = num[7:0];
    assign overflow = (a[7] && b[7] && (!num[7])) || ((!a[7]) && (!b[7]) && num[7]);

endmodule
